Random and deterministic test generation methods, plus sequential circuit test generation.
Verilog is used to describe the internal architectures of Built-In Self-Test (BIST) and Design for Testability (DFT) . This helps engineers evaluate hardware overhead and timing feasibility, which is critical for System-on-Chip (SoC) designs. Digital System Test and Testable Design: Using ...
Logic BIST basics, test pattern generation, and output response analysis. Logic BIST basics, test pattern generation, and output
Memory fault models, MBIST (Memory BIST) methods, and functional procedures. Unlike traditional texts, it uses Verilog HDL to
The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology
Are you interested in a specific from the book, like BIST or Boundary Scan , for a more detailed breakdown? Courses Syllabus – Monsoon 2024 - pgadmissions@iiit.ac.in